1. Technical Field
The present invention relates to silicon-on-insulator circuits in general, and in particular to a method and apparatus for improving silicon-on-insulator complementary metal-oxide-semiconductor circuits. Still more particularly, the present invention relates to a method and apparatus for improving device matching and switching point tolerance in silicon-on-insulator cross-coupled complementary metal-oxide-semiconductor circuits.
2. Description of the Prior Art
In recent years, the predominant processing technology for integrated circuits has been the bulk complementary metal-oxide-semiconductor (CMOS) technology using silicon as substrates. Although bulk CMOS technology offers various advantages, such as low power consumption and stability, over other types of processing technologies, there are also several drawbacks associated with CMOS circuits, such as relatively slow speed and potential latchup problem. In light of such, a new processing technology called Silicon-on-Insulator (SOI) technology has emerged. Instead of using an semiconductor substrate like the bulk CMOS technology, SOI utilizes an insulating substrate, which provides tremendous improvements in certain circuit characteristics, such as speed and latch-up, over bulk CMOS technology. A detailed description of SOI technology can be found in Weste and Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd ed., pp. 125-130, Addison Wesley (1995), the pertinent portion of which is incorporated herein by reference.
For SOI circuits having transistors in a dual-rail cross-coupled configuration, mismatch and lack of symmetry of transistors on each rail can be attributed to body potential or threshold voltage differentials in transistor characteristics. The body potential is dependent upon the operating history of a circuit. The mismatch and lack of symmetry is also a direct result of dissimilar time constants to discharge the bodies of the transistors compared to the actual circuit access or cycle times. This disclosure describes an apparatus for improving device matching and switching point tolerance in SOI cross-coupled circuits.